DIGITAL EUROPE – DIGITAL-JU-CHIPS-2025-SG-SSOI – 2025

Objectives

• To develop industrial-grade sSOI substrates with reduced defect density to enhance electron mobility and overall device performance, supporting current (22FDX, 18nm) and future (7nm by 2030) FD-SOI technologies
• To establish scalable, cost-effective manufacturing processes aligned with industrial standards for broad adoption
• To demonstrate the integration of strained NMOS and relaxed PMOS regions for balanced transistor performance
• To accelerate the transition from research to industrial-scale production through a pre-industrial infrastructure capable of producing thousands of wafers annually
• To build demonstrators showcasing the advantages of sSOI-based FD-SOI over FinFET technologies, particularly in RF performance, noise reduction, and power efficiency
• To provide open access to Process Design Kits (PDKs) and differentiated design blocks, including stress and relaxation features, to support innovation in FD-SOI
• To enable early-stage design validation and system integration through Multi-Project Wafer (MPW) runs, supporting high-speed RF, mmWave radar, automotive, and IoT applications as part of the Next Gen FD-SOI roadmap

Priorities

• Priority 1: To create a sustainable accelerator open to all European stakeholders, providing access to cutting-edge sSOI technologies and manufacturing capabilities
• Priority 2: To develop and standardize Process Design Kits (PDKs) based on validated sSOI data, enabling optimized system-level designs and supporting the transition to 7nm FD-SOI by 2030
• Priority 3: To scale sSOI substrate production to industrial levels, ensuring low defect densities and high manufacturing yields
• Priority 4: To drive the development of intellectual property and reinforce Europe’s industrial capacity and leadership in critical semiconductor technologies
• Priority 5: To foster synergies with the FD-SOI pilot line and other Chips JU pilot lines, strengthening collaboration and innovation across the European semiconductor ecosystem
• Priority 6: To deliver comprehensive training and skills development programs for European technologists and engineers in sSOI integration and advanced semiconductor manufacturing

Among financed actions

• Development of industrial-grade sSOI substrates
• Defect reduction and improved electron mobility
• Compatibility with existing FD-SOI processes
• Integration of strained NMOS and relaxed PMOS
• Scale-up to industrial production (thousands of wafers/year)
• Demonstrators comparing sSOI vs. FinFET
• Open access to Process Design Kits (PDKs)
• Validation via Multi-Project Wafer (MPW) runs
• Support for RF, radar, IoT, and automotive designs
• Training and upskilling of technical workforce

Eligibility

• Be a public or private entity
• Be a non-profit making entity
• Be: a NGO, a company, a university, a research institution, a SME, an organisation…
• Be established in one of the eligible countries:
  • EU Member States (including overseas countries and territories)
  • Non-EU states: listed EEA countries
• A consortium composed of maximum 70 applicant can be constituted

Additional information

• Contact: calls@chips-ju.europa.eu

Useful

• Guidelines: Click here
• Other call documents: Click here
• DG website: Click here
• More information: Click here

• Total budget of the call: 30 million euros
• Funding rate: between 25% and 35% of the total eligible costs